The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to an asymmetric data path position and delays technique enabling high speed access in integrated circuit memory devices.
Many types of DRAM based devices are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”), DDR3 DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell generally comprises a single access transistor coupled to an associated capacitor (i.e. a 1T/1C design) that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bitlines interconnecting rows of these cells.
In some conventional DRAM designs, the column field of the memory banks is sub-divided by the pre-fetch size. However, since the pre-fetch can start with any address within the pre-fetch field, there can be no preference in the physical placement of the column field within the bank. That is, that portion of the column pre-field which is physically the farthest away will determine the worst case, or slowest, access time.